Thin film transistor

ABSTRACT

A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a nano-scale semiconductor structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims all benefits accruing under 35 U.S.C. § 119 fromChina Patent Application No. 201710051903.6, filed on Jan. 20, 2017, inthe China Intellectual Property Office, the contents of which are herebyincorporated by reference.

FIELD

The present disclosure relates to a Schottky diode.

BACKGROUND

A Schottky diode has low power, high current and super high speed,therefore, it can be applied in various of electronic devices. TheSchottky diode generally includes a noble metal and a semiconductorlayer contacted with the noble metal. A barrier having a rectifyingproperty is formed in an interface between the noble metal and thesemiconductor layer. The Schottky diode is often used in a transistor.

For low-dimensional nano-electronic materials, unlike traditionalsilicon materials, it is difficult to prepare diodes by doping method.The conventional nano-semiconductor diode material is mainly obtained bychemical doping or heterojunction, the preparation process is complex,and the application of the diode is limited.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations of the present technology will now be described, by wayof example only, with reference to the attached figures, wherein:

FIG. 1 is a structure schematic side view of a first embodiment of aSchottky diode.

FIG. 2 is a side structure sectional view of the Schottky diode in FIG.1.

FIG. 3 is a side structure sectional view of a Schottky diode in anotherexample.

FIG. 4 is a structure schematic side view of one embodiment of aSchottky diode array.

FIG. 5 is a structure schematic top view of one embodiment of a Schottkydiode, in which a one-dimensional nano-material is used as asemiconductor structure.

FIG. 6 is a structure schematic top view of one embodiment of a Schottkydiode, in which a two-dimensional nano-material is used as asemiconductor structure.

FIG. 7 is a Scanning electron micrograph (SEM) image of a carbonnanotube array film according to one embodiment.

FIG. 8 is a structure schematic view of the carbon nanotube horizontalarray film in FIG. 7.

FIG. 9 is an SEM image of a carbon nanotube network according to oneembodiment.

FIG. 10 is a current-voltage graph of a Schottky diode according to oneembodiment.

FIG. 11 is a structure schematic sectional view of a second embodimentof a Schottky diode.

FIG. 12 is a structure schematic sectional view of a second embodimentof a Schottky diode according to one example.

FIG. 13 is a structure schematic sectional view of a second embodimentof a Schottky diode according to another example.

FIG. 14 is a structure schematic sectional view of a second embodimentof a Schottky diode including an insulating substrate.

FIG. 15 is a structure schematic sectional view of one embodiment of aSchottky diode array.

FIG. 16 a structure schematic side view of a third embodiment of a thinfilm transistor.

FIG. 17 is a transfer characteristic diagram of a thin film transistoraccording to one embodiment.

FIG. 18 is a structure schematic side view of a fourth embodiment of athin film transistor.

DETAILED DESCRIPTION

The disclosure is illustrated by way of example and not by way oflimitation in the figures of the accompanying drawings in which likereferences indicate similar elements. It should be noted that referencesto “another,” “an,” or “one” embodiment in this disclosure are notnecessarily to the same embodiment, and such references mean “at leastone.”

It will be appreciated that for simplicity and clarity of illustration,where appropriate, reference numerals have been repeated among thedifferent figures to indicate corresponding or analogous elements. Inaddition, numerous specific details are set forth in order to provide athorough understanding of the embodiments described herein. However, itwill be understood by those of ordinary skill in the art that theembodiments described herein can be practiced without these specificdetails. In other instances, methods, procedures, and components havenot been described in detail so as not to obscure the related relevantfeature being described. Also, the description is not to be consideredas limiting the scope of the embodiments described herein. The drawingsare not necessarily to scale, and the proportions of certain parts havebeen exaggerated to illustrate details and features of the presentdisclosure better.

Several definitions that apply throughout this disclosure will now bepresented.

The term “substantially” is defined to be essentially conforming to theparticular dimension, shape, or other feature which is described, suchthat the component need not be exactly or strictly conforming to such afeature. The term “include,” when utilized, means “include, but notnecessarily limited to”; it specifically indicates open-ended inclusionor membership in the so-described combination, group, series, and thelike.

Referring to FIGS. 1-2, one embodiment is described in relation to aSchottky diode 100. The Schottky diode 100 includes an insulatingsubstrate 102 and a Schottky diode unit (not labeled). The Schottkydiode unit is disposed on a surface of the insulating substrate 102 andsupported by the insulating substrate 102. The Schottky diode unitincludes a first electrode 104, a semiconductor structure 108, and asecond electrode 106. The first electrode 104 is disposed on the surfaceof the insulating substrate 102. The semiconductor structure 108includes a first end 1082 and a second end 1084 opposite to the firstend 1082. The first end 1082 of the semiconductor structure 108 is laidon the first electrode 104, and the first electrode 104 is locatedbetween the first end 1082 of the semiconductor structure 108 and theinsulating substrate 102. The second end 1084 is disposed on the surfaceof the insulating substrate 102, and the second electrode 106 isdisposed on the semiconductor structure 108, and the second end 1084 ofthe semiconductor structure 108 is located between the second electrode106 and the insulating substrate 102.

Referring to FIG. 3, in one embodiment, the structure of the Schottkydiode 100 can be shown in FIG. 3. The first electrode 104 is embedded inthe insulating substrate 102, and an upper surface of the firstelectrode 104 is flush with the surface of the insulating substrate 102.The semiconductor structure 108 is horizontally disposed on the surfaceof the insulating substrate 102. The first end 1082 is located on theupper surface of the first electrode 104. The second electrode 106 isdisposed on the surface of the semiconductor structure 108 to cover thesecond end 1084 of the semiconductor structure 108. The first electrode104 is located between the first end 1082 of the semiconductor structure108 and the insulating substrate 102. The second end 1084 of thesemiconductor structure 108 is between the second electrode 106 and theinsulating substrate 102.

Referring to FIG. 4, the present invention further provides a Schottkydiode array 10 according to one embodiment. The Schottky diode array 10includes the insulating substrate 102 and a plurality of Schottky diodeunits 110 disposed on the surface of the insulating substrate 102. Theplurality of Schottky diode units 110 are arranged in an array on thesurface of the insulating substrate 102. Each Schottky diode unit 110 isspaced apart from each other. The Schottky diode unit 110 is the same asthe Schottky diode unit described in the first embodiment.

According to one embodiment, the Schottky diode 100 can be obtained by amethod of: forming the first electrode 104 on the insulating substrate102; forming the semiconductor structure 108 on the first electrode 104and the insulating substrate 102, that is, the first end 1082 of thesemiconductor structure 108 is disposed on the upper surface of thefirst electrode 104, and the second end 1084 is disposed on the surfaceof the insulating substrate 102; forming the second electrode 106 is onthe upper surface of the second end 1084 of the semiconductor structure108. In this embodiment, both the first electrode 104 and the secondelectrode 106 are formed by photolithography method.

According to one embodiment, the Schottky diode array 10 is obtained bymethod of: forming a plurality of first electrodes 104 on the insulatingsubstrate 102; forming a plurality of semiconductor structures 108 onthe first electrodes 104 and the insulating substrate 102, the pluralityof semiconductor structures 108 and the plurality of first electrodes104 are arranged in a one-by-one manner, that is, the first end 1082 ofeach semiconductor structure 108 is disposed on the upper surface of oneof the first electrodes 104 and the second end 1084 is disposed on thesurface of the insulating substrate 102; forming the second electrode106 above the second end 1084 of the semiconductor structure 108, thesemiconductor structure 108 and the second electrode 106 are arranged ina one-by-one manner, thereby a plurality of second electrodes 106 areformed. Each second electrode 106 is disposed above the second end 1084of one of the semiconductor structures 108, the second end 1084 islocated between one second electrode 106 and the insulating substrate102. The plurality of first electrodes 104 and the plurality of secondelectrodes 106 are formed by photolithography.

The insulating substrate 102 is used to support Schottky diode 100 orthe Schottky diode array 10. A material of the insulating base 102 isselected from hard materials and flexible materials. The hard materialcan be glass, quartz, ceramic, diamond, or silicon. The flexiblematerial can be plastic or resin. In this embodiment, the material ofthe insulating substrate 102 is a silicon wafer with a silicon dioxidelayer. The insulating substrate 102 can also be a Large scale integratedcircuit board, and the plurality of Schottky diodes 100 may beintegrated on one insulating substrate 102 according to a predeterminedpattern to form a thin film transistor or other semiconductor device.

A material of the first electrode 104 or the second electrode 106 can bealuminum, copper, tungsten, molybdenum, gold, titanium, neodymium,palladium, cesium or alloys thereof. In this embodiment, the material ofthe first electrode 104 and the second electrode 106 is a palladiumfilm, which has a thickness of about 50 nanometers.

In some embodiments, the semiconductor structure 108 is a nano-scalesemiconductor structure. The nano-scale semiconductor structure may be aone-dimensional nano-structure, that is, a linear structure with adiameter less than 200 nanometers as shown in FIG. 5. In anotherexample, the nano-scale semiconductor structure may also be atwo-dimensional nano-structure, that is a film-like structure with athickness less than 200 nanometers, as shown in FIG. 6. A material ofthe semiconductor structure 108 can be an N-type semiconductor or aP-type semiconductor. The material of the semiconductor structure 108 isnot limited, and can be an inorganic compound semiconductor, anelemental semiconductor or an organic semiconductor material. In detail,the material of the semiconductor structure 108 can be gallium arsenide,silicon carbide, polysilicon, monocrystalline silicon or naphthalene.The one-dimensional nano-structure can be nanowire, nanotube or nanorod,such as carbon nanotube and silicon nanowire. When the semiconductorstructure 108 is a one-dimensional nanostructure, the semiconductorstructure 108 extends from the first electrode 104 to the secondelectrode 106. The two-dimensional nano-structure can be nanofilm, suchas carbon nanotube film, molybdenum disulfide film or the like. In someembodiments, the material of the semiconductor structure 108 is atransition metal sulfide material. In this embodiment, the material ofthe semiconductor structure 108 is molybdenum sulfide (MoS₂), which isan N-type semiconductor material and has a thickness ranged from 1nanometer (nm) to 2 nm.

The semiconductor structure 108 can be a carbon nanotube structure. Thecarbon nanotube structure can be a single semiconducting carbon nanotubeor a carbon nanotube film. A thickness of the carbon nanotube film isless than or equal to 200 nanometers.

In one embodiment, the semiconductor structure 108 is a singlesemiconducting carbon nanotube, as shown in FIG. 5. The semiconductingcarbon nanotube can have a diameter ranged from about 1 nm to 10 nm. Insome embodiment, the semiconducting carbon nanotube is a single-walledcarbon nanotube having a diameter ranged from 1 nm to 5 nm, and a lengthranged from 100 nm to 1 μm. The semiconducting carbon nanotube extendsfrom the first electrode 104 to the second electrode 106. One end of thesemiconducting carbon nanotube is disposed on the first electrode 104,and the other end of the semiconducting carbon nanotube is disposedunder the second electrode 106.

In other embodiments, the semiconductor structure 108 is a carbonnanotube film including a plurality of carbon nanotubes. In theplurality of carbon nanotubes, a mass percent of semiconducting carbonnanotubes is ranged from about 80% to about 100%. The semiconductorstructure 108 can insist of the plurality of carbon nanotubes. Thecarbon nanotube film can be an ordered carbon nanotube film or adisordered carbon nanotube film. In the ordered carbon nanotube film,the plurality of carbon nanotubes in the carbon nanotube film arearranged orderly. In the disordered carbon nanotube film, the pluralityof carbon nanotubes are arranged disorderly.

Referring to FIG. 7 and FIG. 8, in one embodiment, the ordered carbonnanotube film 112 is a carbon nanotube horizontal array film including aplurality of carbon nanotubes 1122 arranged substantially parallel toeach other and horizontally arranged. The plurality of carbon nanotubes1122 are parallel to the surface of the insulating substrate 102 andextends from the first electrode 104 to the second electrode 106. Theordered carbon nanotube film 112 is directly grown by a CVD method ortransferred from a carbon nanotube array to a target substrate to form aplurality of carbon nanotube conductive channels. The ordered carbonnanotube film 112 includes only one single carbon nanotube 1122 in thethickness direction. That is, a thickness of the ordered carbon nanotubefilm 112 is the same as a diameter of one carbon nanotube 1122. Thecarbon nanotube 1122 can have a diameter ranged from 1 nm to 10 nm. Theordered carbon nanotube film 112 has a thickness ranged from 1 nm to 10nm. In some embodiments, the carbon nanotube 1122 is single-walledcarbon nanotube having a diameter ranged from 1 nm to 5 nm, and a lengthof 100 nm to 1 μm.

Referring to FIG. 9, in some embodiments, the disordered carbon nanotubefilm is a carbon nanotube network. The carbon nanotube network includesa plurality of carbon nanotubes arranged randomly. In the carbonnanotube network, a mass percentage of the semiconducting carbonnanotubes is greater than or equal to 80% and less than or equal to100%. The carbon nanotube network can only include carbon nanotubes. Theplurality of carbon nanotubes are crossed with or be parallel to eachother. The plurality of carbon nanotubes are semiconducting carbonnanotubes having a diameter ranged from 1 nm to 50 nm. The carbonnanotube network has a thickness ranged from 1 nm to 100 nm. In someembodiments, the carbon nanotube network can be obtained bysolution-immersed carbon nanotubes deposition. The method of depositingand immersing the carbon nanotubes in the solution includes steps of:dispersing carbon nanotube powder in a dispersant, wherein a masspercentage of the semiconducting carbon nanotubes in the carbon nanotubepowder is greater than or equal to 80% and less than or equal to 100%,the dispersant is an organic solvent such as NMP, toluene and the like;then a target substrate is immersed into the dispersant to deposit adisordered network of carbon nanotubes, ie, a carbon nanotube network onthe surface of the target substrate. In this embodiment, the targetsubstrate is the insulating substrate 102 formed with a first electrode104. The carbon nanotubes are deposited directly on the surface of thefirst electrode 104 and the surface of the insulating substrate 102 toform the carbon nanotube film. Then, the second electrode 106 is formedon the other end of the carbon nanotube film far away from the firstelectrode 104 to obtain a structure as shown in FIG. 1. That is, thecarbon nanotube film is the semiconductor structure 108. In anotherembodiment, the carbon nanotube film can be formed by ink-jet printing.The ink-jet printing carbon nanotube means that the carbon nanotubepowder dispersed in the dispersant is prepared into a printing ink, andthe printing ink is printed directly on the first electrode 104 and theinsulating substrate 102 to get the carbon nanotube film. In thisembodiment, the carbon nanotube film is directly printed on theinsulating substrate 102 on which the first electrode 104 is formed. Inanother embodiment, the carbon nanotube film is a disordered networkobtained by CVD growth using a metal catalyst and a carbon source. Thecatalyst metal includes iron, cobalt, nickel and their correspondingalloys, salts and the like. The carbon source includes gases and liquidssuch as methane, acetylene, carbon monoxide, ethanol and isopropanol.

In one embodiment, the ordered carbon nanotube film can be a drawncarbon nanotube film. The drawn carbon nanotube film is a free standingstructure consisting a plurality of carbon nanotubes, wherein a masspercentage of the semiconducting carbon nanotubes in the carbon nanotubepowder is greater than or equal to 80% and less than or equal to 100%.The drawn carbon nanotube film includes a number of successive andoriented carbon nanotubes joined end-to-end by van der Waals attractiveforce therebetween. Each drawn carbon nanotube film includes a number ofsuccessively oriented carbon nanotube segments joined end-to-end by vander Waals attractive force therebetween. Each carbon nanotube segmentincludes a number of carbon nanotubes substantially parallel to eachother, and joined by van der Waals attractive force therebetween. Somevariations can occur in the drawn carbon nanotube film. The carbonnanotubes in the drawn carbon nanotube film are oriented along apreferred orientation. The drawn carbon nanotube film is a free standingstructure means that the drawn carbon nanotube film does not need alarge area support, and as long as the opposite sides of the drawncarbon nanotube film are supported, the drawn carbon nanotube film canbe dangled as a whole to maintain its own film state, the drawn carbonnanotube film can be hung in the air by using two supporters separatelysupports its opposite sides. The free standing character of the drawncarbon nanotube film is achieved mainly through the continuous presenceof carbon nanotubes joined with each other by van der Waals attractiveforce therebetween in the drawn carbon nanotube film.

In other embodiments, the carbon nanotube film can be a pressed carbonnanotube film. The pressed carbon nanotube film is a free standingstructure including a plurality of carbon nanotubes, wherein a masspercentage of the semiconducting carbon nanotubes in the carbon nanotubepowder is greater than or equal to 80% and less than or equal to 100%.The pressed carbon nanotube film is formed by pressing a carbon nanotubearray. The carbon nanotubes in the pressed carbon nanotube film arearranged along a same direction or along different directions. Thecarbon nanotubes in the pressed carbon nanotube film can rest upon eachother. Adjacent carbon nanotubes are attracted to each other and arejoined by van der Waals attractive force. An angle between a primaryalignment direction of the carbon nanotubes and a surface of the pressedcarbon nanotube film is about 0 degrees to approximately 15 degrees. Thegreater the pressure applied, the smaller the angle obtained. In oneembodiment, the carbon nanotubes in the pressed carbon nanotube film arearranged along different directions, the carbon nanotube structure canbe isotropic. The pressed carbon nanotube film includes a plurality ofmicro-pores dispersed uniformly, and dimeters of the plurality ofmicro-pores can be ranged from 1 nm to 0.5 μm.

The Schottky diode 100 provided by the present invention has a specialasymmetric structure. That is, the first electrode 104 is located abovethe semiconductor structure 108 and the second electrode 106 is locatedbelow the semiconductor structure 108. No matter the semiconductorstructure 108 is a P-type semiconductor or an N-type semiconductor, aSchottky barrier height of the semiconductor structure 108 above theelectrode is greater than a Schottky barrier height of the semiconductorstructure 108 below the electrode. Therefore, the Schottky diode withasymmetric structure provided by the present invention, due to itsspecial asymmetric structure, can have a good Schottky diodesperformance with simple semiconductor materials without complicatedchemical doping or Heterojunction methods using more materials. In thepresent invention, for a P-type Schottky diode using P-typesemiconductor structure 108, a current flowing in a direction from thefirst electrode 104 located above the semiconductor structure 108 to thesecond electrode 106 located below the semiconductor structure 108 isgreater than a current flowing in a direction from the second electrode106 located below the semiconductor structure 108 to the first electrode104 above the semiconductor structure 108, as such, when the currentflows from the first electrode 104 to the second electrode 106, theSchottky diode 100 is turned on; when the current flows from the seconddirection 106 to the first electrode 104, the Schottky diode 100 isturned off. For a N-type Schottky diode using N-type semiconductorstructure 108, a current flowing in a direction from the secondelectrode 106 located below the semiconductor structure 108 to the firstelectrode 104 located above the semiconductor structure 108 is greaterthan a current flowing in a direction from the first electrode 104located above the semiconductor structure 108 to the second electrode106 below the semiconductor structure 108, as such, when the currentflows from the second electrode 106 to the first electrode 104, theSchottky diode 100 is turned on; when the current flows from the firstdirection 104 to the second electrode 106, the Schottky diode 100 isturned off. The above phenomenon is due to the flow of electrons andholes. When the electrons and the holes flows along a same direction,the direction of the current caused by the flowing of electrons isdifferent from the direction of the current caused by the flowing of theholes.

FIG. 10 is a current-voltage graph of a Schottky diode according to oneembodiment. In the present embodiment, a molybdenum disulfide (MoS₂)nano-film is used as the semiconductor structure 10. As can be seen fromFIG. 10, the Schottky diode has a good directivity, the ratio ofpositive and negative voltage can reach 10⁴.

The Schottky diode provided by the invention has the followingadvantages: firstly, a Schottky diode with better rectification effectcan be obtained by adopting a special asymmetric structure, in which asimple semiconductor material without doping is used, and the ratio ofthe positive voltage and the negative voltage can reach 10⁴; second, dueto the semiconductor structure has a simple structure, the preparationmethod is easy to do, the cost of Schottky diode is reduced and can beprepared in large-scale.

Referring to FIG. 11, FIG. 12 or FIG. 13, according to a secondembodiment of the present invention, a Schottky diode 200 is provided.The Schottky diode 200 includes a first electrode 204, a secondelectrode 206, and a semiconductor structure 208. The semiconductorstructure 208 includes a first end 2082 and a second end 2084 oppositeto the first end 2082. The first end 2082 of the semiconductor structure208 contacts with the first electrode 204, and the second end 2084contacts with and the second electrode 206. The first electrode 204includes a first metal layer 204 a and a second metal layer 204 b. Thefirst metal layer 204 a covers the second metal layer 204 b. One end ofthe second metal layer 204 b is extended from the first metal layer 204a to form a step structure 212 in the first electrode 204. The secondelectrode 206 includes a third metal layer 206 a and a fourth metallayer 206 b. The third metal layer 206 a covers the fourth metal layer206 b. One end of the third metal layer 206 a protrudes from the fourthmetal layer 206 b to form an inverted step structure 214. The first end2082 of the semiconductor structure 208 is a portion of thesemiconductor structure 208 that is sandwiched by the first metal layer204 a and the second metal layer 204 b. The second end 2084 of thesemiconductor structure 208 is a portion of the semiconductor structure208 that is sandwiched by the third metal layer 206 a and the fourthmetal layer 206 b. A portion of the semiconductor structure 108 betweenthe first end 2082 and the second end 2084 is defined as a middleportion (not labeled). The step structure 212 and the inverted stepstructure 214 are both located between the first end 2082 and the secondend 2084 of the semiconductor structure 208, and near the middle portionof the semiconductor structure 208. It can be seen from FIG. 11, FIG. 12or FIG. 13, the middle portion of the semiconductor structure 208extends from the step structure 212 of the first electrode 204 to theinverted step structure 214 of the second electrode 206.

Materials of the first electrode 204 and the second electrode 206 arethe same as the first electrode 104 and the second electrode 106 in thefirst embodiment.

Structures and materials of the semiconductor structure 208 are the sameas the semiconductor structure 108 in the first embodiment.

The Schottky diode 200 can further include an insulating substrate forsupporting the first electrode 204, the second electrode 206, and thesemiconductor structure 208. The structure of the insulating substrateis not limited, and can be a sheet with a planar surface. The Schottkydiode 200 is located on the surface of the insulating substrate.Referring to FIG. 14, the insulating substrate 202 may be a substratewith a grooved structure. The second metal layer 204 b of the firstelectrode 204 and the fourth metal layer 206 b of the second electrode206 are embedded in the insulating substrate 202. Surfaces of the secondmetal layer 204 b, the fourth metal layer 206 b, and the insulatingsubstrate 202 are a plane. The semiconductor structure 208 is located onthe plane.

Other characteristics of the Schottky diode 200 are the same as theSchottky diode 100 disclosed above.

In a method for making the Schottky diode 200 according to oneembodiment, the second metal layer 204 b and the fourth metal layer 206b are formed on the insulating substrate 202 by a photolithographymethod. The first metal layer 204 a and the third metal layer 206 a areformed on the semiconductor structure 208 by photolithography method.

Referring to FIG. 15, an embodiment of the present invention furtherprovides a Schottky diode array 20. The Schottky diode array 20 includesan insulating substrate 202 and a plurality of Schottky diode units 210.The plurality of Schottky diode units 210 are uniformly distributed on asurface of the insulating substrate 202. Characteristics of the Schottkydiode unit 210 are the same as the Schottky diode 200 disclosed above.

Referring to FIG. 16, a third embodiment of the present inventionprovides a thin film transistor 300. The thin film transistor 300includes a gate electrode 302, an insulating medium layer 304 and atleast one Schottky diode unit 110. The thin film transistor 300 caninclude one or more than one Schottky diode units 110. The insulatingmedium layer 304 is located on a surface of the gate electrode 302. Theat least one Schottky diode unit 110 is located on a surface of theinsulating medium layer 304. The at least one Schottky diode unit 110 isinsulated from the gate electrode 302 via the insulating medium layer304.

The gate electrode 302 is a conductive film. The conductive film has athickness ranged from 0.5 nm to 100 μm. A material of the conductivefilm may be metal, alloy, doped semiconductor (such as silicon), indiumtin oxide (ITO), antimony tin oxide (ATO), conductive silver paste,conductive polymer or conductive carbon nanotube. The metal or alloymaterial may be aluminum, copper, tungsten, molybdenum, gold, titanium,neodymium, palladium, cesium, or any alloy thereof. In this embodiment,the gate electrode 302 is a metal palladium film and has a thickness of50 nm.

The insulating medium layer 304 functions as a support and an insulator.A material of the insulating medium layer 304 is hard materials orflexible materials. The hard materials can be glass, quartz, ceramics,diamond, or oxide. The flexible materials can be plastics or resins. Inthis embodiment, the material of the insulating medium layer 304 is anALD-grown aluminum oxide film with a thickness of 20 nanometers.

The thin film transistor 300 can include a plurality of Schottky diodeunits 110. The insulating medium layer 304 can be a substrate with alarge-scale integrated circuit, and the plurality of Schottky diodeunits 110 are integrated on the insulating medium layer 304 according toa predetermined rule or pattern, to form a thin film transistor panel orother thin film transistor semiconductor device. A shape of theinsulating medium layer 304 is not limited, and can be a planarstructure. The Schottky diode unit 110 is disposed on a surface of theinsulating medium layer 304. The insulating medium layer 304 may also bea substrate having a grooved structure, the first electrode and thesecond electrode of the Schottky diode unit 110 are embedded inside theinsulating medium layer 304 so that the surfaces of the first electrode104, the second electrode 106 and the insulating dielectric layer 304are in a same plane.

Other characteristics of the Schottky diode unit 110 are the same as theSchottky diode 100 disclosed above.

In one embodiment, a P-type carbon nanotube material is employed as thesemiconductor structure 108. When a voltage of −1 V is applied to thefirst electrode 104, and the gate 302 is scanned with different voltage,a graph of current and voltage obtained is shown as I₁ in FIG. 17; whena voltage of −1 volt is applied to the second electrode 106, and thegate 302 is scanned with different voltage, a graph of current andvoltage obtained is shown as I₂ in FIG. 17. It can be seen from FIG. 17that when the thin film transistor 300 is in ON-state, the currentflowing from the first electrode 104 located above the semiconductorstructure 108 to the second electrode 106 located below thesemiconductor structure 108 is greater than the current flowing from thesecond electrode 106 located below the semiconductor structure 108 tothe first electrode 104 located above the semiconductor structure 108,that is, I₁ is greater than I₂.

In other embodiments, the thin film transistor 300 includes a pluralityof Schottky diode units 110, and the plurality of Schottky diode units110 are separated from each other and located on the surface of theinsulating medium layer 304.

Referring to FIG. 18, a fourth embodiment of the present inventionprovides a thin film transistor 400. The thin film transistor 400includes a gate electrode 402, an insulating medium layer 404, and atleast one Schottky diode unit 210. The thin film transistor 400 mayinclude one or more Schottky diode units 210. The gate electrode 402 isthe same as the gate electrode 302 disclosed in the third embodiment.The insulating medium layer 404 is the same as the insulating mediumlayer 304 disclosed in the third embodiment. The Schottky diode unit 210is the same as the Schottky diode unit 210 disclosed in the secondembodiment.

The insulating medium layer 404 may be a planar plate structure, and theSchottky diode unit 210 is disposed on a surface of the insulatingmedium layer 404. The insulating medium layer 404 may also be asubstrate with groove structures. In the Schottky diode unit 210, thesecond metal layer 204 b of the first electrode 204 and the fourth metallayer 206 b of the second electrode 206 are embedded in the insulatingmedium layer 404, so that the surfaces of the second metal layer 204 b,the fourth metal layer 206 b and the insulating dielectric layer 404 arein a same plane.

In one embodiment, a P-type carbon nanotube material is used as thesemiconductor structure 108. When the thin film transistor 300 is inon-state, the current flowing from the first electrode 104 located abovethe semiconductor structure 108 to a position below the semiconductorstructure 108 is greater than the current flowing from the secondelectrode 106 located below the semiconductor structure 108 to the firstelectrode 104 above the semiconductor structure 108.

It is to be understood that the above-described embodiments are intendedto illustrate rather than limit the present disclosure. Variations maybe made to the embodiments without departing from the spirit of thepresent disclosure as claimed. Elements associated with any of the aboveembodiments are envisioned to be associated with any other embodiments.The above-described embodiments illustrate the scope of the presentdisclosure but do not restrict the scope of the present disclosure

Depending on the embodiment, certain of the steps of a method describedmay be removed, others may be added, and the sequence of steps may bealtered. The description and the claims drawn to a method may includesome indication in reference to certain steps. However, the indicationused is only to be viewed for identification purposes and not as asuggestion as to an order for the steps.

What is claimed is:
 1. A thin film transistor comprising: a gateelectrode, an insulating medium layer and at least one Schottky diodeunit, wherein the insulating medium layer is located on the gateelectrode, the at least one Schottky diode unit is located on a surfaceof the insulating medium layer and insulated from the gate electrode viathe insulating medium layer, each of the at least one Schottky diodeunit comprises: a first electrode located on the surface of theinsulating medium layer, wherein the first electrode comprises a firstmetal layer and a second metal layer, the first metal layer covers thesecond metal layer, one end of the second metal layer is extended fromthe first metal layer to form a step structure in the first electrode; asecond electrode located on the surface of the insulating medium layerand apart from the first electrode, wherein the second electrodecomprises a third metal layer and a fourth metal layer, the third metallayer covers the fourth metal layer, one end of the third metal layerprotrudes from the fourth metal layer to form an inverted stepstructure; and a semiconductor structure comprising a first end and asecond end, wherein the first end of the semiconductor structure issandwiched by the first metal layer and the second metal layer, thesecond end of the semiconductor structure is sandwiched by the thirdmetal layer and the fourth metal layer, a portion of the semiconductorstructure between the first end and the second end is defined as amiddle portion, the step structure of the first electrode and theinverted step structure of the second electrode are both located betweenthe first end and the second end of the semiconductor structure, andnear the middle portion of the semiconductor structure, thesemiconductor structure is a nano-scale semiconductor structure.
 2. Thethin film transistor of claim 1, wherein the nano-scale semiconductorstructure is a one-dimensional nano-structure with a diameter less than200.
 3. The thin film transistor of claim 2, wherein the one-dimensionalnano-structure comprises nanowire, nanotube and nanorod.
 4. The thinfilm transistor of claim 1, wherein the nano-scale semiconductorstructure is a two-dimensional nano-structure with a thickness less than200 nanometers.
 5. The thin film transistor of claim 4, wherein thetwo-dimensional nano-structure is a carbon nanotube film or molybdenumdisulfide film.
 6. The thin film transistor of claim 1, wherein amaterial of the semiconductor structure is a transition metal sulfidematerial.
 7. The thin film transistor of claim 6, wherein the materialof the semiconductor structure 108 is molybdenum sulfide (MoS₂).
 8. Thethin film transistor of claim 7, wherein the molybdenum sulfide is anN-type semiconductor material and has a thickness ranged from 1nanometer to 2 nanometers.
 9. The thin film transistor of claim 1,wherein the semiconductor structure is an N-type semiconductor or aP-type semiconductor.
 10. The thin film transistor of claim 1, wherein amaterial of the semiconductor structure is gallium arsenide, siliconcarbide, polysilicon, monocrystalline silicon or naphthalene.
 11. Thethin film transistor of claim 1, wherein the surface of the insulatingmedium layer is a planar surface.
 12. The thin film transistor of claim1, wherein the surface of the insulating medium layer is a groovedstructure, the second metal layer of the first electrode and the fourthmetal layer of the second electrode are embedded in the insulatingsubstrate, surfaces of the second metal layer, the fourth metal layer,and the insulating substrate are a plane, and the semiconductorstructure is located on the plane.
 13. The thin film transistor of claim1, wherein the at least one Schottky diode unit comprises a plurality ofSchottky diode units, the plurality of Schottky diode units are arrangedin an array and separated from each other.
 14. The thin film transistorof claim 1, wherein the gate electrode is a metal palladium film with athickness of 50 nm.